On the Difficulty of Building a Precise Timing Model for Real-Time Programming

For real-time computing it is important to know the worstcase execution time (WCET) of all time-critical software operations in order to ensure timeliness of the system. The calculation of a precise upper bound of the WCET relies on the availability of an adequate timing model of the target hardware. Within this article we explore the different mechanisms of modern processors that lead to complex timing models. We explore the different types of memory elements within a processor that resemble the state of the processor. Further, we compare the compile-time knowledge and run-time knowledge and discuss the consequences of offline (compiler) and online (hardware) code optimization. The main consequence of this hardware exploration is that real-time computing needs co-design of compilation, timing analysis, and processor optimizations to improve temporal predictability of the system.